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19-0659; Rev 1; 1/08
KIT ATION EVALU BLE AVAILA
4V to 72V Input LDOs with Boost Preregulator
General Description
The MAX5092A/MAX5092B/MAX5093A/MAX5093B lowquiescent-current, low-dropout (LDO) regulators contain simple boost preregulators operating at a high frequency. The devices seamlessly provide a preset 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B) LDO output voltage from an automotive cold-crank through load-dump (3.5V to 80V) input voltage conditions. The MAX5092_/MAX5093_ deliver up to 250mA with excellent load and line regulation. During normal operation, when the battery is healthy, the boost preregulator is completely turned off, reducing quiescent current to 65A (typ). This makes the devices suitable for always-on power supplies. The buck-boost operation achieved by this combination of LDO and boost preregulator offers the advantage of using a single off-the-shelf inductor in place of the multiple-winding custom magnetics needed in typical single-ended primary inductor converter (SEPIC) and transformer-based flyback topologies. The high operating frequency of the boost regulator significantly reduces component size. The MAX5092_ integrates a blocking diode to further reduce the external component count. The boost preregulator output voltage is preset to 7V. Both LDO and boost output voltages are programmable using external resistors. The boost preregulator output voltage is adjustable up to 11V (MAX5092_), or up to 12V (MAX5093_). The LDO output voltage is adjustable from 1.5V to 9V (MAX5092_) or from 1.5V to 10V (MAX5093_). The devices feature a shutdown mode with 5A (typ) shutdown current, a HOLD input to implement a self-holding circuit, and a power-on-reset output (RESET) with an externally programmable timeout period. Additional features include output overload, short-circuit, and thermal protection. The MAX5092_/MAX5093_ are available in a thermally enhanced, 16-pin 5mm x 5mm thin QFN package and can dissipate up to 2.7W at +70C on a multilayer PC board (PCB).
Features
o Wide Operating Input Voltage Range: 3.5V to 72V with a 4V Startup Voltage o LDO Output Regulates to 5V Seamlessly from an Input Voltage of 3.5V to 72V o Up to 250mA Output Current o Preset 3.3V, 5V, or Externally Programmable LDO Output Voltage from 1.5V to 9V (MAX5092_) or from 1.5V to 10V (MAX5093_) o Preset 7V or Externally Programmable Boost Output Voltage Up to 11V (MAX5092_) or Up to 12V (MAX5093_) o 65A Quiescent Current in LDO Mode (VIN 8V) o 5A Shutdown Current o Power-On Reset (RESET) with Programmable Timeout Period o Output Short-Circuit and Thermal Protection o TQFN Package Capable of Dissipating Up to 2.7W at +70C
MAX5092/MAX5093
Ordering Information
PART MAX5092AATE+ MAX5092BATE+ MAX5093AATE+ MAX5093BATE+ TEMP RANGE PINPACKAGE PKG CODE T1655-3 T1655-3 T1655-3 T1655-3
-40C to +125C 16 TQFN-EP* -40C to +125C 16 TQFN-EP* -40C to +125C 16 TQFN-EP* -40C to +125C 16 TQFN-EP*
+Denotes lead-free package. *EP = Exposed pad.
Pin Configuration
PGND_BST
TOP VIEW
12
11
10
BSOUT 9
LX
LX
BSFB 13 VL 14 CT 15 RESET 16
8 7
OUT OUT_SENSE SET PGND_LDO
Applications
Automotive--Body Electronics Automotive--ECU Industrial
MAX5092_/ MAX5093_ +
1 IN 2 EN 3 SGND 4 HOLD
6 5
Typical Operating Circuit and Selector Guide appear at end of data sheet.
THIN QFN (5mm x 5mm)
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
ABSOLUTE MAXIMUM RATINGS
IN, EN, LX, BSOUT to SGND..................................-0.3V to +80V PGND_BST, PGND_LDO to SGND .......................-0.3V to +0.3V RESET, OUT, OUT_SENSE to SGND .....................-0.3V to +12V BSOUT to LX (MAX5092_)......................................-0.3V to +12V VL, SET, BSFB, SGND..............................................-0.3V to +6V HOLD to SGND........................................-0.3V to (VOUT + 0.3V) CT to SGND.................................................-0.3V to (VVL + 0.3V) OUT Current (IOUT) Short Circuit to PGND_LDO, (VIN 28V) ..............................................................Continuous Note 1: As per JEDEC Standard 51 (Multilayer Board). RESET Sinking Current .........................................................5mA Continuous Power Dissipation (TA = +70C) 16-Pin Thin QFN (derate 33.3mW/C above +70C)...............................................2666mW (Note 1) Operating Temperature Range .........................-40C to +125C Maximum Junction Temperature .....................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VEN = 14V, IOUT = 1mA, CIN = 47F, CBSOUT = 22F, COUT = 10F, CVL = 1F, TA = TJ = -40C to +125C, unless otherwise noted. See Figures 4-7 as applicable. Typical specifications are at TA = +25C.) (Note 2)
PARAMETER INPUT SUPPLY Input Voltage Range Internal Input Undervoltage Lockout Supply Current (Boost Converter Off) Supply Current (Boost Converter On) Shutdown Supply Current BOOST CONVERTER Minimum BSOUT Output Current Boost Converter Enable Threshold Boost Converter Disable Threshold Boost Converter Disable Hysteresis BSOUT Output Voltage Maximum BSOUT Output Voltage BSFB Regulation Voltage BSFB Input Bias Current Boost Internal Switch On-Resistance Boost Internal Switch Minimum Off-Time IBSOUT VBST_EN VBST_DIS VBST_HYS VBSOUT VBSOUT(MAX) VBSFB IBSFB RDS(ON) tOFF 0.80 0.5 1 VIN = 4V, BSFB = SGND, VOUT = 5V MAX5092_ MAX5093_ 1.18 VIN = 4V VBSOUT - VOUT falling (Note 5) VBSOUT - VOUT rising (Note 5) 1.7 2.2 250 2.0 2.5 0.5 7.00 11 12 1.24 1.30 100 1.2 1.25 2.3 2.8 mA V V V V V V nA s VIN VUVLOF VUVLOR IQ (Note 3) VIN falling VIN rising LDO mode, IOUT = 100A TJ = -40C to +125C (Note 4) 4 3.0 3.4 3.2 3.6 65 70 0.4 TJ = -40C to +125C (Note 4) 6 72 3.4 3.8 85 100 1.0 10 mA A V V SYMBOL CONDITIONS MIN TYP MAX UNITS
A
LDO mode, IOUT = 250mA IS ISHDN VIN = 5V VEN +0.4V
2
_______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 14V, IOUT = 1mA, CIN = 47F, CBSOUT = 22F, COUT = 10F, CVL = 1F, TA = TJ = -40C to +125C, unless otherwise noted. See Figures 4-7 as applicable. Typical specifications are at TA = +25C.) (Note 2)
PARAMETER Boost Internal Switch Maximum On-Time Internal Switch Current Limit Boost Turn-On Response Time Internal Diode Forward Voltage Drop LDO Guaranteed Output Current IOUT VBSOUT - VOUT = 2V (Note 6) SET = SGND, MAX5092A/ MAX5093A Output Voltage VOUT SET = SGND, MAX5092B/ MAX5093B Minimum Adjustable Output Voltage Maximum Adjustable Output Voltage VADJMIN IOUT = 1mA 100A IOUT 250mA IOUT = 1mA 100A IOUT 250mA 250 3.25 3.2 4.900 4.85 3.3 3.3 5 5 1.5 9 V 10 1.5 0.9 200 0.4 0.5 1.6 1.205 1.235 0.5 IOUT = 1mA to 250mA f = 100Hz Power-Supply Rejection Ratio PSRR f = 1MHz Short-Circuit Current ISC IOUT = 10mA, VBSOUT(AC) = 500mVP-P, VOUT = 5V IOUT = 10mA, VBSOUT(AC) = 500mVP-P, VOUT = 5V 255 0.2 80 dB 60 490 mA 1.265 100 0.6 V nA mV/mA mV/V 10.0 1.6 V V s 3.35 3.4 5.075 5.10 V V mA VF SYMBOL tON-MAX ILIM Measured in steady-state condition Time from VBSOUT falling below regulation to switch on-time MAX5092_ only, IF = 1A CONDITIONS MIN 1.80 1.5 2 0.95 TYP 2.25 MAX 2.70 3.0 5 UNITS s A s V
MAX5092/MAX5093
Boost operation, VIN = 4V, VBSOUT = 7V MAX5092_, VBSOUT = 11V MAX5093_, VBSOUT = 12V
VADJMAX
Boost operation, VIN = 4V
Adjustable Output Voltage Dropout Voltage LDO Startup Response Time
VADJ VDO
LDO operation, VIN VBST_DIS (boost converter off) (Note 7) IOUT = 250mA (Note 8) Rising edge of VBSOUT to the rising edge of VOUT, RL = 500, SET = SGND
Line Regulation SET Reference Voltage SET Input Bias Current Load Regulation
VOUT / VIN VSET ISET VOUT / IOUT
7V VIN 72V, ILOAD = 10mA
MAX5092A/MAX5093A MAX5092B/MAX5093B
7V VIN 28V, ILOAD = 250mA
_______________________________________________________________________________________
3
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VEN = 14V, IOUT = 1mA, CIN = 47F, CBSOUT = 22F, COUT = 10F, CVL = 1F, TA = TJ = -40C to +125C, unless otherwise noted. See Figures 4-7 as applicable. Typical specifications are at TA = +25C.) (Note 2)
PARAMETER ENABLE, HOLD and RESET EN High Input Threshold EN Low Input Threshold EN Input Bias Current HOLD Low Input Threshold HOLD Release Voltage HOLD Pullup Current RESET Voltage Threshold RESET Threshold Hysteresis RESET Output Low Voltage RESET Output High Leakage Current RESET Output Minimum Timeout Period EN to RESET Minimum Timeout Delay Delay Comparator Threshold (Rising) Delay Comparator Threshold Hysteresis CT Charge Current CT Discharge Current Thermal Shutdown Temperature Threshold Thermal Shutdown Temperature Hysteresis VCTTH VCTTH-HYS ICT-CHG ICT-DIS TJ(SHDN) TJ(HYST) Temperature rising 1.5 ENH ENL IEN VIL VIH IHOLD VRESET VRHYST VRL IRH Regulator on, EN transition from high to low EN = low Internally connected to OUT % of VOUT, VOUT falling % of VOUT ISINK = 1mA V R ESET = 5V CCT not connected CCT not connected 1.205 25 260 1.24 100 2 5 165 20 2.5 1.265 87 VOUT 0.4 4 90 2 0.4 1 92 0.25 2.4 0.4 2 0.4 V V A V V A % % V A s s V mV A mA C C SYMBOL CONDITIONS MIN TYP MAX UNITS
Limits at -40C are guaranteed by design and characterization; not production tested. Guaranteed minimum operating voltage is 3.5V on VIN falling only. Guaranteed by design and not production tested. The boost converter disable threshold (VBST_DIS) is a static measurement. Internal comparator delay may cause a higher disable level. Note 6: The continuous maximum output current from the LDO is guaranteed according to the maximum power dissipation imposed by the package thermal constraints. Note 7: Maximum output adjustable value is conditioned by the maximum adjustable BSOUT Output Voltage Range minus the maximum dropout across the pass transistor. Note 8: Dropout voltage is defined as (VBSOUT - VOUT) when VOUT is 2% below the value of VOUT for VBSOUT = VOUT + 2V. Note 2: Note 3: Note 4: Note 5:
4
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4V to 72V Input LDOs with Boost Preregulator
Typical Operating Characteristics
(VIN = VEN = 14V, CIN = 47F, CBSOUT = 22F, COUT = 10F, CVL = 1F, TA = +25C, unless otherwise noted.) (See Figures 4-7 as applicable.)
QUIESCENT SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5092B)
MAX5092/93 toc01
MAX5092/MAX5093
INPUT CURRENT (IIN) vs. INPUT VOLTAGE (MAX5092B)
MAX5092/93 toc02
QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (MAX5092B)
BOOST CONVERTER NOT SWITCHING, QUIESCENT SUPPLY CURRENT = IIN - IOUT
MAX5092/93 toc03
90 QUIESCENT SUPPLY CURRENT (A) 85 80 75 70 65 60 55 50 8 16 24 32 40 48 56 64 BOOST CONVERTER NOT SWITCHING, QUIESCENT SUPPLY CURRENT = IIN - IOUT IOUT = 10mA IOUT = 100A
100 IOUT = 10mA INPUT CURRENT (mA) 10
100 QUIESCENT SUPPLY CURRENT (A) 90 80 IOUT = 10mA 70 60 50 40
1
IOUT = 100A
IOUT = 100A
BOOST CONVERTER SWITCHING 0.1 4.0 4.5 5.0 5.5 6.0 6.5 7.0 INPUT VOLTAGE (V) -40 -15 10 35 60 85 110 135
72
INPUT VOLTAGE (V)
TEMPERATURE (C)
QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (MAX5093B)
MAX5092/93 toc04
SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5092B)
MAX5092/93 toc05
SHUTDOWN SUPPLY CURRENT vs. INPUT VOLTAGE (MAX5093B)
SHUTDOWN SUPPLY CURRENT (A)
MAX5092/93 toc06
100 QUIESCENT SUPPLY CURRENT (A) 90 80 70 60 50 40 -40 -15 10 35 60 85 110 IOUT = 100A IOUT = 10mA BOOST CONVERTER NOT SWITCHING, QUIESCENT SUPPLY CURRENT = IIN - IOUT
10 SHUTDOWN SUPPLY CURRENT (A)
10
8
8
6
6
4
4
2 VEN = 0V 0
2 VEN = 0V 0
135
4
14
24
34
44
54
64
74
4
14
24
34
44
54
64
74
TEMPERATURE (C)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5092B)
MAX5092/93 toc07
SWITCHING WAVEFORMS VBSOUT PROGRAMMED < (VOUT + VBST_DIS)
MAX5092/93 toc08
10 SHUTDOWN SUPPLY CURRENT (A)
VIN 1V/div VBSOUT 2V/div
5V (AC-COUPLED) 8.5V (AC-COUPLED)
8
6 VOUT 100mV/div 4 VEN = 0V 2 -40 -15 10 35 60 85 110 135 TEMPERATURE (C) ILX 2A/div 100s/div 5V (AC-COUPLED)
VIN = 5V, IOUT = 100mA, VBSOUT PROGRAMMED TO 11V
0
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5
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Typical Operating Characteristics (continued)
(VIN = VEN = 14V, CIN = 47F, CBSOUT = 22F, COUT = 10F, CVL = 1F, TA = +25C, unless otherwise noted.) (See Figures 4-7 as applicable.)
LINE-TRANSIENT RESPONSE (VIN STEP FROM 4V TO 7V)
MAX5092/93 toc09
LINE-TRANSIENT RESPONSE (VIN STEP FROM 3.5V TO 72V)
MAX5092/93 toc10
IOUT = 250mA VOUT 50mV/div 5V (AC-COUPLED) 7V VOUT 50mV/div 4V VIN 50V/div
IOUT = 5mA
72V 3.5V
VIN 1V/div
5V (AC-COUPLED)
72V VBSOUT 1V/div 200s/div 7V (AC-COUPLED) VBSOUT 50V/div 40ms/div 7V
SWITCHING WAVEFORMS VBSOUT PROGRAMMED < (VOUT + VBST_DIS)
MAX5092/93 toc11
LINE-TRANSIENT RESPONSE (VIN STEP FROM 3.5V TO 14V)
MAX5092/93 toc12
VIN 1V/div VBSOUT 2V/div
5V (AC-COUPLED) 7V (AC-COUPLED) VOUT 100mV/div 5V (AC-COUPLED) 14V VBSOUT 5V/div 7V 14V VIN 5V/div 0 100s/div 200s/div 3.5V
VOUT 100mV/div
5V (AC-COUPLED) VIN = 5V, IOUT = 100mA, VBSOUT PROGRAMMED TO 7V
ILX 2A/div
DROPOUT VOLTAGE (VBSOUT - VOUT) vs. LDO LOAD CURRENT
MAX5092/93 toc13
LDO OUTPUT VOLTAGE vs. LDO LOAD CURRENT (MAX5092B)
MAX5092/93 toc14
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
0
MAX5092/93 toc15
1000
5.15 5.10 LDO OUTPUT VOLTAGE (V) 5.05 5.00 4.95 4.90 4.85 TA = +135C, VIN = 4V TA = +135C, VIN = 14V 0 100 200 TA = -40C: CIN = 10F, CBSOUT = 4.7F, COUT = 10F (CERAMIC) TA = +25C, +135C: CIN = 47F, CBSOUT = 22F (ELECTROLYTIC), COUT = 10F (CERAMIC) TA = +25C, VIN = 4V TA = +25C, VIN = 14V
VIN = 14V, IOUT = 10mA
DROPOUT VOLTAGE (mV)
800
TA = -40C, VIN = 4V TA = -40C, VIN = 14V
PSRR (dB)
600
10dB/div
400 200 0 0 50 100 150 200 250 LDO LOAD CURRENT (mA)
-70
300
100
1k
10k FREQUENCY (Hz)
100k
1M
LDO LOAD CURRENT (mA)
6
_______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
Typical Operating Characteristics (continued)
(VIN = VEN = 14V, CIN = 47F, CBSOUT = 22F, COUT = 10F, CVL = 1F, TA = +25C, unless otherwise noted.) (See Figures 4-7 as applicable.) POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
0
MAX5092/93 toc16
MAX5092/MAX5093
STARTUP THROUGH INPUT VOLTAGE
MAX5092/93 toc17
VIN = 8V, IOUT = 10mA VIN 10V/div
IOUT = 250mA
0V PSRR (dB) VBSOUT 10V/div 10dB/div ILX 5A/div VOUT 5V/div 100 1k 10k FREQUENCY (Hz) 100k 1M 100s/div 0V
-70
0A
0V
SHUTDOWN THROUGH VIN
MAX5092/93 toc18
STARTUP THROUGH ENABLE
MAX5092/93 toc19
VIN 10V/div
IOUT = 250mA 0V
VIN 10V/div VBSOUT 10V/div
14V
14V
VBSOUT 10V/div
0V VOUT 5V/div VEN 2V/div 200s/div
ILX 1A/div VOUT 5V/div 2ms/div
0A
0V
0V
IOUT = 250mA
0V
SHUTDOWN THROUGH ENABLE
MAX5092/93 toc20
RESET TIMING RESPONSE
MAX5092/93 toc21
VIN 10V/div VBSOUT 10V/div
14V
VOUT 2V/div
IOUT = 250mA CT = 680pF 0V
14V VRESET 2V/div
VOUT 5V/div VEN 2V/div 200s/div IOUT = 250mA
0V VEN 2V/div 0V 200s/div
0V
0V
_______________________________________________________________________________________
7
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Typical Operating Characteristics (continued)
(VIN = VEN = 14V, CIN = 47F, CBSOUT = 22F, COUT = 10F, CVL = 1F, TA = +25C, unless otherwise noted.) (See Figures 4-7 as applicable.)
VOUT vs. TEMPERATURE (MAX5092B)
MAX5092/93 toc22 MAX5092/93 toc23
VOUT vs. TEMPERATURE
3.36 3.34 3.32 VOUT (V) VOUT (V) 3.30 3.28 4.95 3.26 3.24 -40 -15 10 35 60 85 110 135 TEMPERATURE (C) IOUT = 10mA, R5 = 100k, R4 = 165k, FIGURE 6 5.00 5.10
LDO LOAD-TRANSIENT RESPONSE (MAX5092B)
MAX5092/93 toc24
5.05
VOUT 50mV/div (AC-COUPLED)
IOUT 100mA/div IOUT = 1mA, VSET = 0V 0mA 135 2ms/div
4.90 -40 -15 10 35 60 85 110 TEMPERATURE (C)
INPUT-VOLTAGE STEP RESPONSE
MAX5092/93 toc25
ENABLE AND HOLD TIMING
MAX5092/93 toc26
INTERNAL BOOST DIODE FORWARD DROP (MAX5092)
MAX5092/93 toc27
1500 1250 DIODE VOLTAGE (mV) 0V 1000 750 500 250 0
IOUT = 5mA VEN 5V/div VOUT 20mV/div 5V (AC-COUPLED) V 72V VIN 20V/div
HOLD
5V/div
0V
VOUT 5V/div 3.5V 200ms/div 200ms/div
0V
VIN = 8V, BOOST CONVERTER NOT SWITCHING 0 0.5 1.0 1.5 2.0 2.5 3.0
DIODE CURRENT (A)
BOOST CONVERTER POWER LOSS (VBSOUT = 7V)
MAX5092/93 toc28
BOOST CONVERTER POWER LOSS (VBSOUT = 11V)
MAX5092/93 toc29
GROUND CURRENT DISTRIBUTION (162 UNITS TESTED)
35 30 NUMBER OF UNITS 25 20 15 10 5 0 TA = TJ = +125C TA = TJ = -40C
MAX5092/93 toc30
1.0 TA = +105C: VIN = 3.5V VIN = 4V VIN = 5V
1.2 1.0 POWER LOSS (W) 0.8 0.6 0.4 0.2 0 TA = +105C: VIN = 4V VIN = 5V VIN = 3.5V VIN = 4V
40
0.8 POWER LOSS (W)
0.6
VIN = 3.5V VIN = 5V
0.4 TA = +25C: VIN = 3.5V VIN = 4V VIN = 5V
0.2
0 0 50 100 150 200 250 300 350 IOUT (mA)
0
50
100
150
200
250
300
350
52
54
56
58 60
62
64
66
68 70
IOUT (mA)
IGND (A)
8
_______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
Pin Description
PIN 1 2 3 NAME IN EN SGND FUNCTION Input Supply Voltage. Bypass IN to the power ground plane with a 47F (low-ESR) aluminum electrolytic capacitor in parallel with a 1F ceramic capacitor placed as close to the IC as possible. Enable Input. Drive EN high to turn on the IC. Drive EN low to disable the IC. Connect EN directly to IN for always-on operation. Signal Ground. Connect SGND to the signal ground plane and the exposed paddle. Connect the power ground and signal ground plane together at the negative terminal of the input capacitor(s). Output Hold. When HOLD is forced low, the regulator stores the on-state of the output, allowing the regulator to remain enabled even if EN is pulled low. To shut down the regulator, release HOLD after EN is pulled low. If HOLD is unused, either connect HOLD to OUT or leave unconnected. HOLD is internally connected to OUT through a 4A pullup current. LDO Power Ground. Connect PGND_LDO to the power ground plane. Connect the PGND_LDO ground and signal ground plane together. Feedback Input for the LDO. Connect SET directly to SGND to set the output voltage of the LDO to the preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B). Connect SET to the center tap of a resistor-divider connected between the LDO output and SGND to set the output voltage. VSET regulates to 1.24V when using an adjustable output. LDO Regulator Output. Bypass OUT to the power ground plane with a 10F ceramic capacitor. VOUT regulates to a preset voltage of 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B), or is adjustable from 1.5V to 9V (MAX5902_) or 1.5V to 10V (MAX5093_). Boost Regulator Output Voltage. Bypass BSOUT to the PGND_BST ground plane with a 22F (low-ESR) aluminum electrolytic capacitor in parallel with a 1F ceramic capacitor placed as close to the IC as possible. Connect BSFB directly to SGND to regulate the BOOST output to a fixed voltage of 7V for VIN 7V. VBSOUT follows VIN for VBSOUT - VOUT > 2.5V (typ). VBSOUT is programmable up to 11V (MAX5092_) or 12V (MAX5093_) by connecting BSFB to the center tap of an external resistor-divider connected between the BOOST output and PGND_BST. Inductor Connection to the Drain of the Internal Power MOSFET. Connect LX to the switched side of the inductor. Connect pins 10 and 11 together as close to the device as possible. For the MAX5093, also connect LX to the anode of the external Schottky diode. Boost Regulator Power Ground. Connect PGND_BST to the power ground plane. Connect the PGND_BST ground plane and the signal ground plane together at the negative terminal of the input capacitor(s). Feedback Input for the Boost Regulator. Connect BSFB directly to SGND to set the boost regulator output voltage to 7V. Connect BSFB to the center tap of an external resistor-divider connected between BSOUT and SGND to set the output voltage. VBSFB regulates to 1.24V when using an adjustable output. Internal Regulator Output for IC Supply. Bypass VL to SGND with a 1F/6.3V ceramic capacitor placed as close to the IC as possible. VVL regulates to 5.5V with VBSOUT 5.5V. RESET Timeout Programming Input. Connect a capacitor from CT to SGND to set the RESET timeout period. See the CT Capacitor Selection section. RESET Output. RESET is an open-drain output that goes high impedance when VOUT exceeds 92% of the output voltage threshold after a programmed time delay. RESET pulls low immediately once VOUT drops below 90% of the regulated LDO output voltage. Exposed Paddle. Connect to the signal ground plane (SGND). Connect to a large-signal ground plane for increased thermal performance.
MAX5092/MAX5093
4
HOLD
5
PGND_LDO
6
SET
7 8
OUT_SENSE LDO Regulator Output Sense. Connect OUT_SENSE to OUT at the output capacitor near the load. OUT
9
BSOUT
10, 11
LX
12
PGND_BST
13
BSFB
14 15
VL CT
16
RESET
--
EP
_______________________________________________________________________________________
9
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Functional Diagrams
IN VL INTERNAL LDO IN VL LX LX BSOUT
MAX5092_
1s ONE-SHOT OUT
S
Q
DRIVER
BSOUT
R
Q
CURRENT-LIMITING COMPARATOR
R1
RS 2.25s ONE-SHOT OUT BSOUT VREF VDIS_TH BST_DIS OUT VREF ERROR AMPLIFIER HOLD CONTROL LOGIC, THERMAL SHUTDOWN, AND OVERCURRENT PROTECTION OUT OUT_SENSE R3 LDO OUT IN R2 VPK MUX BSFB
EN
R4 VL MUX SET
CT COMPARATOR
2A
CT DELAY COMPARATOR RESET
0.92 x VREF
SGND
PGND_LDO P
PGND_BST
Figure 1. MAX5092_ Functional Diagram
10 ______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
Functional Diagrams (continued)
IN VL INTERNAL LDO IN VL LX LX BSOUT
MAX5092/MAX5093
MAX5093_
1s ONE-SHOT OUT
S
Q
DRIVER
BSOUT
R
Q
CURRENT-LIMITING COMPARATOR
R1
RS 2.25s ONE-SHOT OUT BSOUT VREF VDIS_TH BST_DIS OUT VREF ERROR AMPLIFIER HOLD CONTROL LOGIC, THERMAL SHUTDOWN, AND OVERCURRENT PROTECTION OUT OUT_SENSE R3 LDO OUT IN R2 VPK MUX BSFB
EN
R4 VL MUX SET
CT COMPARATOR
2A
CT DELAY COMPARATOR RESET
0.92 x VREF
SGND
PGND_LDO P
PGND_BST
Figure 2. MAX5093_ Functional Diagram
______________________________________________________________________________________ 11
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Detailed Description
The MAX5092A/MAX5092B/MAX5093A/MAX5093B include a step-up, switch-mode DC-DC converter and a linear regulator to provide step-up/-down voltage conversion over a wide range of input voltages. This combination of an LDO and a boost converter offers the advantage of using a single off-the-shelf inductor in place of the multiple-winding custom magnetics needed in typical SEPIC or transformer-based flyback topologies. The boost preregulator is completely turned off during normal automotive operation (V IN = 14V), reduces quiescent current to 65A (typ), and makes the devices suitable for always-on power supplies. The devices have an internal UVLO threshold of 3.8V (max, VIN rising) that must be exceeded before the device is enabled. When VIN is above VUVLO, the internal boost converter starts switching and regulates VBSOUT to the programmed boost output voltage. The low quiescent-current LDO steps down VBSOUT to the programmed LDO output voltage. The LDO output is preset to 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B). Both output voltages can be adjusted by using external resistor-dividers. If (VBSOUT - VOUT) rises above 2.5V (typ), the boost converter is disabled, forcing V BSOUT to follow V IN . If VBSOUT - VOUT falls below 2V (typ), the boost converter starts switching and regulates V BSOUT to the programmed voltage. The boost converter regulates VBSOUT for VIN down to 3.5V, providing uninterrupted operation during low cold-crank voltages even if the programmed LDO output voltage is greater than VIN (but less than 9V). The boost converter turn-on response time is less than 10s, making cold-crank input glitches transparent to the system even at full load. The boost-converter output is followed by a high PSRR, low-quiescent-current LDO. The LDO rejects the switching noise present at BSOUT and provides a clean, regulated output voltage. The linear regulator uses an internal p-channel MOSFET pass element. Additional features include a power-on-reset function with an externally adjustable timeout, an enable (EN) input, and a hold (HOLD) regulator control input.
(VBSOUT) section). The MOSFET turns off when the inductor current reaches the peak current limit (2.5A typ) or after 2.25s maximum on-time, whichever occurs first. The MOSFET is held off for at least 1s after the turn-on phase. A new switching cycle initiates once VBSOUT falls below the threshold. In this control scheme, switching frequency and output ripple are functions of load current and input voltage. No frequency compensation is needed in the PFM control scheme. The output of the boost converter is preset to 7V and is adjustable by using external resistors. See the Setting the Boost Output Voltage VBSOUT section. If V BSOUT is programmed greater than (V OUT + VBST_DIS), larger ripple is observed on BSOUT. The reason is as VBSOUT rises above VOUT + VBST_DIS, the boost converter is disabled, causing VBSOUT to fall. As VBSOUT falls to VOUT + VBST_EN, the boost converter turns back on, and VBSOUT rises. For the lowest VBSOUT ripple, program VBSOUT within the boost disable threshold. See the Typical Operating Characteristics for the Switching Waveforms. Due to the integrated blocking diode in the MAX5092_, VBSOUT is limited to 11V. Use the MAX5093_ for higher boost output voltages (or to reduce the power dissipation in to the package). The MAX5093_ requires an external diode for the boost converter. Select the external diode according to the Schottky Diode Selection (MAX5093_) section.
Linear Regulator
The MAX5092_/MAX5093_ contain an internal p-channel MOSFET used as the pass transistor for the LDO. The output of the boost regulator is connected to the source of the p-MOSFET. The LDO starts up 200s after the boost regulator starts up. The LDO supplies up to 250mA with a typical dropout voltage of 0.9V. The maximum LDO output current is determined by the package power-dissipation limit as well as the internal current limit. The LDO is designed to be a low-quiescent-current type. During normal operation when the battery voltage is > 9V, the MAX5092_/MAX5093_ consume only 75A (max) at +85C and 100A load. The output voltage of the LDO is set using the SET input. Connect SET to SGND to use the factory-preset output voltage. Connect SET to the center of an external resistor-divider connected from OUT to SGND to program a different output voltage. See the Setting the LDO Output Voltage (VOUT) section.
Boost Converter
The switch-mode converter uses a minimum off-time, maximum on-time pulse frequency modulation (PFM) control scheme. The internal MOSFET turns on whenever VBSOUT falls below the regulation point determined by VBSFB (see the Setting the Boost Output Voltage
12
______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
Internal Regulator (VL)
An internal regulator (VL) is used to supply all internal low-voltage blocks. Bypass VL to SGND with a 1F ceramic capacitor placed as close to the IC as possible. VVL regulates to 5.5V when VBSOUT is above 5.5V. V VL tracks the voltage at BSOUT when V BSOUT is below 5.5V.
Enable and Hold Inputs
The MAX5092_/MAX5093_ utilize two logic inputs, EN (active-high) and HOLD (active low), to implement a self-holding circuit with no additional components. For example, an automotive ignition switch drives EN high and the regulator turns on. If HOLD is then driven low, the regulator remains on even if EN goes low. As long as HOLD is forced low and remains low after initial regulator power-up, the regulator remains on. From this state, release HOLD (an internal current source connects HOLD to OUT), or connect HOLD to OUT to turn the regulator off. Drive EN low and HOLD high to place the IC into shutdown mode. Shutdown mode reduces supply current to 5A. Figure 3 shows the timing diagram for the enable and hold functions. Table 1 shows the state of the regulator output with respect to the voltage level at EN and HOLD with reference to Figure 3. Connect HOLD to OUT or leave unconnected to disable the hold feature and use EN as a standard on/off control input.
MAX5092/MAX5093
Power-On-Reset Output (RESET)
The MAX5092_/MAX5093_ contain an open-drain output (RESET) that indicates when the LDO output (VOUT) is out of regulation. If the output of the LDO falls below 90% of the nominal output voltage, RESET pulls low after a short delay. Once the output rises above 92% of the nominal output voltage, RESET goes high impedance after the programmed reset timeout period. Connect a 100k pullup resistor from OUT to RESET. See the CT Capacitor Selection section for details on setting the RESET timeout period.
HOLD
EN
OUT
ORDER
1
2
3
4
5
6
Figure 3. Enable and Hold Timing Diagram
Table 1. Truth Table for Enable and Hold Timing Diagram
ORDER 1 2 3 4 5 5 EN Low High Low High Low High HOLD X Released Released Low Released X OUT Off On Off On Off On COMMENTS Initial State. EN has a 500nA pulldown to GND. HOLD has an internal current source to OUT. HOLD follows OUT. Regulator output is active when EN is pulled high. HOLD is in release state, and it follows OUT. HOLD is in release state. OUT follows EN. HOLD is pulled low externally after OUT turns on. The regulator output is forced on regardless of the state of EN. A self-holding state. HOLD is released after EN is pulled low. Output turns off. Regulator enabled. Normal turn-on behavior. Regulator follows EN and HOLD follows OUT.
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13
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Applications Information
L1 4.7H
10 INPUT 4V TO 72V C1* 47F C2* 1F LX 1 IN
11 LX VL 14 C6 1F
U1 MAX5092B
VOUT R1 100k RESET ON OFF 2 EN 16 RESET
BSOUT
9 12 13 C3* 1F
7V C4* 22F
PGND_BST BSFB
HOLD
4
P SIGNAL
3
SGND OUT_SENSE OUT 7 8 C7 10F OUTPUT 5V AT 250mA**
15 C5 0.22F
CT
PGND_LDO
5
VOUT
***
SET
6
P
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE. **OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE. ***SEE PCB LAYOUT GUIDELINES SECTION.
Figure 4. MAX5092B Typical Application Circuit with Factory Preprogrammed LDO and Boost Output Voltages
14
______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
Applications Information (continued)
L1 4.7H
MAX5092/MAX5093
10 INPUT 4V TO 72V C1* 47F C2* 1F LX 1 IN
11 LX VL 14 C6 1F
U1 MAX5093B
VOUT R1 100k RESET ON OFF 2 EN 16 RESET
BSOUT
9 12 13 C3* 1F
7V C4* 22F
PGND_BST BSFB
HOLD
4
P SIGNAL
3
SGND OUT_SENSE OUT 7 8 C7 10F OUTPUT 5V AT 250mA**
15 C5 0.22F ***
CT
PGND_LDO
5
VOUT
SET
6
P
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE. **OUTPUT CURRENT IS LIMITED BY THE TOTAL POWER-DISSIPATION CAPABILITY OF THE PACKAGE. ***SEE PCB LAYOUT GUIDELINES SECTION.
Figure 5. MAX5093B Typical Application Circuit with Factory Preprogrammed Boost and LDO Output Voltages
______________________________________________________________________________________
15
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Applications Information (continued)
L1 4.7H
10 INPUT 4V TO 72V C1* 47F C2* 1F LX 1 IN
11 LX VL 14 C6 1F OUTPUT 5.3V C3* 1F C4* 22F R1 1.65M 5.5V
U1 MAX5092A
VOUT R3 100k RESET ON OFF 2 EN 16 RESET
BSOUT
9 12 13 4
PGND_BST BSFB
HOLD
P SIGNAL
R2 499k
3
SGND OUT_SENSE OUT
VOUT 7 8 C7 10F OUTPUT 3.3V**
15 C5 0.22F
CT
PGND_LDO
5
***
SET
6
P
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE. **OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE. ***SEE PCB LAYOUT GUIDELINES SECTION.
Figure 6. MAX5092A Typical Application Circuit with User-Programmed LDO and Boost Output Voltages
16
______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
Applications Information (continued)
L1 4.7H
MAX5092/MAX5093
10 INPUT 4V TO 72V C1* 47F C2* 1F LX 1 IN
11 LX VL 14 C6 1F OUTPUT 12V C3* 1F C4* 22F R1 4.32M
U1 MAX5093A
VOUT R3 100k RESET ON OFF 2 EN 16 RESET
BSOUT
9 12 13 4
PGND_BST BSFB
HOLD
P SIGNAL
R2 499k
3
SGND OUT_SENSE OUT
VOUT 7 8 C7 10F OUTPUT 10V**
15 *** C5 0.22F
CT
PGND_LDO
5
R4 698k
SET
6 R5 100k
P
*THESE CAPACITORS MUST BE RATED AT THE HIGHEST VIN VOLTAGE. **OUTPUT CURRENT IS LIMITED BY THE TOTAL OUTPUT POWER AND THE DISSIPATION CAPABILITY OF THE PACKAGE. ***SEE PCB LAYOUT GUIDELINES SECTION.
Figure 7. MAX5093A Typical Application Circuit with User-Programmable Boost Output Voltage and LDO Output Voltage
______________________________________________________________________________________
17
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Design Guidelines
Input Capacitor (CIN) and Boost Capacitor (CBSOUT) Selection
The input current waveform of the boost converter is continuous, and usually does not demand high capacitance at its input. However, the MAX5092_/MAX5093_ boost converter is designed to fully turn on as soon as the input drops below a certain voltage in order to ride out cold-crank droops. This operation demands low input source impedance for proper operation. If the source (battery) is located far from the IC, high-capacity, low-ESR capacitors are recommended for CIN. The worst-case peak capacitor current could be as high as 3A. Use a 47F, 100m low-ESR capacitor placed as close as possible to the input of the device. Note that the aluminum electrolytic capacitor ESR increases significantly at cold temperatures. In the cold temperature case, choose an electrolyte capacitor with ESR lower than 40m or connect a low-ESR ceramic capacitor (10F) in parallel with the electrolytic capacitor. The boost converter output (BSOUT) is fed to the input of the internal 250mA LDO. The boost-converter output current waveform is discontinuous and requires highcapacity, low-ESR capacitors at BSOUT to ensure low VBSOUT ripple. During the on-time of the internal MOSFET, the BSOUT capacitor supplies 250mA current to the LDO input. During the off-time, the inductor dumps current into the output capacitor while supplying the output load current. The internal 250mA LDO is designed with high PSRR; however, high-frequency spikes may not be rejected by the LDO. Thus, high-value, low-ESR electrolytic capacitors are recommended for C BSOUT . Peak-to-peak VBSOUT ripple depends on the ESR of the electrolyte capacitor. Use the following equation to calculate the required ESR (ESR BSOUT) of the BSOUT capacitor: ESRBSOUT = VESRBS ILIM - IOUT where VESRBS is 75% of total peak-to-peak ripple at BSOUT, ILIM is the internal switch current limit (3A max), and IOUT is the LDO output current. Use a 100m or lower ESR electrolytic capacitor. Make sure the ESR at cold temperatures does not cause excessive ripple voltage. Alternately, use a 10F ceramic capacitor in parallel with the electrolyte capacitor. During the switch on-time, the BSOUT capacitor discharges while supplying IOUT. The ripple caused by the capacitor discharge (VCBS) is estimated by using the following equation: I x 2.7 x 10-6 VCBS = OUT CBSOUT where IOUT is the LDO output current and CBSOUT is the BSOUT capacitance.
Inductor Selection
The control scheme of the MAX5092/MAX5093 permits flexibility in choosing an inductor value. Smaller inductance values typically offer smaller physical size for a given series resistance, allowing the smallest overall circuit dimensions. Circuits using larger inductance may provide higher efficiency and exhibit less ripple, but also may reduce the maximum output current. This occurs when the inductance is sufficiently large to prevent the LX current limit (I LIM ) from being reached before the maximum on-time (tON-MAX) expires. For maximum output current, choose the inductor value so that the controller reaches the current limit before the maximum on-time is reached: V xt - L IN ON MAX ILIM where tON-MAX is typically 2.25s, and the current limit (I LIM ) is a maximum of 3A (see the Electrical Characteristics). Choose an inductor with the maximum saturation current (ISAT) greater than 3A.
18
______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
Setting the Boost Output Voltage (VBSOUT)
The MAX5092_/MAX5093_ feature Dual ModeTM operation for the internal boost converter output voltage. These devices operate in a preset output-voltage mode or an adjustable output-voltage mode. In preset mode, internal trimmed feedback resistors set VBSOUT to a fixed 7V. Select the preset mode by directly connecting BSFB to SGND (Figures 4 and 5). Ensure a low-impedance path between BSFB and SGND to limit the transient at BSFB to below 100mV. In adjustable mode, connect BSFB to the center tap of an external resistordivider connected between BSOUT and SGND to program VBSOUT (Figures 6 and 7). Program (VBSOUT < VOUT + VBST_DIS) for lower VBSOUT ripple. Note that the current drawn by the resistor-divider at BSOUT adds to the quiescent current and the shutdown current of the IC. Use the resistor-divider only if VBSOUT is required to be significantly different than 7V. Select 499k or lower resistance value for the bottom resistor (R2) of the divider connected to SGND. The top resistor (R1) value is calculated as: V R1 = R2 x BSOUT - 1 VBSFB where VBSFB is the regulation voltage at BSFB (1.24V typ) and V BSOUT is the desired output voltage for BSOUT.
Schottky Diode Selection (MAX5093_)
The MAX5093_ requires an external diode connected between LX and BSOUT (Figures 5 and 7). Proper selection of an external diode can offer a lower forwardvoltage drop and a higher reverse-voltage handling capability. Since the high switching frequency of the IC demands a high-speed rectifier, Schottky diodes are recommended for most applications because of their fast recovery time and low forward-voltage drop. Ensure that the diode's peak current rating is greater than or equal to the peak current limit of internal boost converter MOSFET. A diode average forward current rating of at least 1A is recommended. Additionally, the diode reverse breakdown voltage must be greater than the worst-case load-dump-condition voltage.
MAX5092/MAX5093
CT Capacitor Selection
The MAX5092_/MAX5093_ contain an open-drain power-on-reset output (RESET) that indicates when the LDO output voltage (VOUT) is out of regulation. When VOUT rises above 92% of the nominal output voltage, RESET goes high impedance after a user-programmable time delay. This time duration is programmable by a capacitor (CCT) from CT to SGND (Figures 4-7). For a chosen RESET active timeout period (tDELAY), calculate the required capacitor value as: CCT = 2 x 10 -6 x tDELAY 1.24
Setting the LDO Output Voltage (VOUT) The LDO output voltage is also Dual Mode (preset and adjustable). Preset mode is selected by connecting SET to SGND (Figures 4 and 5). In preset mode, VOUT regulates to 3.3V (MAX5092A/MAX5093A) or 5V (MAX5092B/MAX5093B) by internal trimmed feedback resistors. Adjustable mode is selected by connecting SET to the center tap of an external resistor-divider connected between OUT and SGND (Figures 6 and 7). Note that the current drawn by the resistor-divider at OUT adds to the quiescent current of the LDO. Use the resistor-divider only if VOUT is required to be significantly different than the preset voltage. Select 100k or lower value for the bottom resistor (R5) of the divider connected to SGND. The top resistor (R4) value is calculated as:
V R4 = R5 x OUT - 1 VSET where VSET is the regulation voltage at SET (1.24V typ) and VOUT is the desired output voltage for the LDO output.
When VOUT drops below 90% of the LDO output regulation voltage, a 5mA pulldown current from CT to SGND discharges CCT. The time required to discharge CT determines the delay necessary to pull RESET low. This delay provides glitch immunity to the RESET function. The glitch immunity delay is directly proportional to the CT capacitor and is approximately 70s for a 0.1F capacitor at CT.
Dual Mode is a trademark of Maxim Integrated Products, Inc.
19
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4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
MAXIMUM POWER DISSIPATION vs. AMBIENT TEMPERATURE
MAXIMUM POWER DISSIPATION (W)
MAX5092/93 fig08
3.0 2.5 2.0 1.5 1.0 0.5 0
PDISS includes the losses in the boost converter operation and the LDO itself. The boost converter loss PLOSS(BST), depends on VIN, VBSOUT, and IOUT. See the Boost Converter Power Loss graphs in the Typical Operating Characteristics to estimate the losses at a given VIN and VBSOUT at room temperature. At a higher ambient temperature of +105C, PLOSS(BST) increases by up to 20% due to higher RDS-ON and switching losses of the internal boost converter MOSFET. (Note: IOUT_MAX must be less than 250mA).
PCB Layout Guidelines
Good PCB layout and routing are required in high-frequency switching power supplies to achieve proper regulation and stability. It is strongly recommended that the evaluation kit PCB layouts be followed as closely as possible. Refer to the MAX5092 EV kit for an example layout. Follow these guidelines for good PCB layout: 1) For SGND, use a large copper plane under the IC and solder it to the exposed paddle. To effectively use this copper area as a heat exchanger between the PCB and ambient, expose this copper area on the top and bottom side of the PCB. Do not make a direct connection from the EP copper plane to pin 3 (SGND) underneath the IC so as to minimize ground bounce. 2) Isolate the power components and high-current path from the sensitive analog circuit. 3) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. 4) Connect the return terminals of input capacitors and boost output capacitors to the PGND_BST power ground plane. Connect the power ground (PGND_BST) and signal ground (SGND) planes together at the negative terminal of the input capacitors. Do not connect them anywhere else. Connect PGND_LDO ground plane to SGND ground plane at a single point. 5) Ensure that the feedback connections are short and direct. Ensure a low-impedance path between BSFB and SGND to limit the transient at BSFB to 100mV. 6) Route high-speed switching nodes away from the sensitive analog areas. Use the internal PCB layer for SGND as an EMI shield to keep radiated noise away from the IC, feedback dividers, and bypass capacitors.
-40 -25 -10 5 20 35 50 65 80 95 110 125 AMBIENT TEMPERATURE (C)
Figure 8. MAX5092/MAX5093 Package Power Dissipation
Maximum Output Current (IOUT_MAX) The MAX5092_/MAX5093_ high input voltage (+72V max) provides up to 250mA of current from OUT. Package power-dissipation limits the amount of output current available for a given input/output voltage and ambient temperature. Figure 8 depicts the maximum power-dissipation curve for the devices. The graph assumes that the exposed metal pad of the IC package is soldered to the PCB copper according to the JEDEC 51 standard (multilayer board). Use Figure 8 to determine the allowable package dissipation for a given ambient temperature. Alternately, use the following formula to calculate the allowable package dissipation (PDISS) in watts: For TA +70C: PDISS = 2.67 For +70C < TA +125C: PDISS = 2.67 - (0.0333 x (TA - 70)) where +70C < TA +125C and 0.0333W/C is the package thermal derating. After determining the allowable package dissipation, calculate the maximum output current (IOUT_MAX) using the following formula:
IOUT _ MAX = PDISS - PLOSS(BST) VIN - VOUT
where PDISS is the allowable package power dissipation and PLOSS(BST) is the boost converter power loss.
20
______________________________________________________________________________________
4V to 72V Input LDOs with Boost Preregulator
Typical Operating Circuit
MAX5092/MAX5093
INPUT 4V TO 72V IN
LX
LX VL
MAX5092B
VOUT BSOUT +7V OUTPUT
RESET OUTPUT ENABLE
PGND_BST RESET BSFB EN HOLD SGND OUT_SENSE OUT +5V OUTPUT VOUT
* CT PGND_LDO P P SET
*SEE PCB LAYOUT GUIDELINES SECTION.
Selector Guide
PART MAX5092AATE+ MAX5092BATE+ MAX5093AATE+ MAX5093BATE+ PRESET LDO OUTPUT (V) 3.3 5 3.3 5 ADJUSTABLE LDO OUTPUT Yes Yes Yes Yes PRESET BSOUT OUTPUT (V) 7 7 7 7 ADJUSTABLE BSOUT OUTPUT Yes Yes Yes Yes BOOST DIODE Internal Internal External External
Chip Information
PROCESS: BiCMOS
______________________________________________________________________________________
21
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
22
______________________________________________________________________________________
QFN THIN.EPS
4V to 72V Input LDOs with Boost Preregulator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX5092/MAX5093
______________________________________________________________________________________
23
4V to 72V Input LDOs with Boost Preregulator MAX5092/MAX5093
Revision History
REVISION NUMBER 0 1 REVISION DATE 10/06 1/08 Initial release Updated Ordering Information and Electrical Characteristics table, added two tocs, updated Functional Diagrams and Applications Diagrams, added boost converter details DESCRIPTION PAGES CHANGED -- 1-12, 14-17, 19, 22, 23
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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